1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having a trench-type device isolation region.
2. Description of the Background Art
Completely independent control of a plurality of devices included in a semiconductor integrated circuit requires the elimination of electrical interference between the devices. To eliminate the electrical interference, it is necessary to form a device isolation region for defining an active region wherein each of the devices is formed.
An example of the methods of forming the device isolation region includes a well-known trench isolation technique. The trench isolation technique is such that a trench is formed in a semiconductor substrate and filled with an insulating film to form a device isolation region. The trench isolation technique provides few trench-type device isolation regions that encounter a problem known as a bird's beak, as compared with the LOCOS (local oxidation of silicon) technique, for example, which is one of the methods of forming the device isolation regions. Thus, the trench isolation technique is essential for size reduction of semiconductor integrated circuits.
FIG. 20 is a plan view of a background art semiconductor device. In FIG. 20, the reference numeral 20 designates a trench-type device isolation region; 3 designates active regions; and 4 designates gate electrode interconnect lines formed over the trench-type device isolation region 20 and the active regions 3. One MOS transistor is formed in each of the active regions 3.
A method of fabricating the background art semiconductor device is described below with reference to FIGS. 21 through 30. FIGS. 21 through 29 are cross-sectional views taken along the line 29--29 of FIG. 20. FIG. 30 is a cross-sectional view taken along the line 30--30 of FIG. 20.
First, a silicon oxide film 6 is formed on a surface of a semiconductor substrate 1, and a silicon nitride film 8 is formed on the silicon oxide film 6 (FIG. 21).
The silicon nitride film 8 and the silicon oxide film 6 are sequentially patterned using a photolithographic pattern as a mask to form a trench 9 extending from the top surface of the silicon nitride film 8 and having a bottom within the semiconductor substrate 1 (FIG. 22).
An inner wall oxide film 6a is formed on the inner wall of the trench 9 by thermal oxidation (FIG. 23).
An insulating film 2 of silicon oxide is formed over the top surface of the structure shown in FIG. 23 by the CVD process (FIG. 24).
Part of the insulating film 2 which is above the top surface of the silicon nitride film 8 is removed by the CMP process using the silicon nitride film 8 as a stopper so that the insulating film 2 is left only in the trench 9 (FIG. 25).
The silicon nitride film 8 is removed by etching using phosphoric acid at elevated temperatures. Then, an insulating film 2a of silicon oxide is deposited over the top surface of the resultant structure by the CVD process (FIG. 26).
The insulating film 2a is partially removed by anisotropic etching so that the insulating film 2a is left only on the sidewalls of the insulating film 2 above the surface of the silicon oxide film 6 (FIG. 27).
The silicon oxide film 6 is removed by etching using hydrofluoric acid (FIG. 28). The inner wall oxide film 6a and the insulating film 2 form the trench-type device isolation region 20. The top surface of the insulating film 2 is raised above the surface of the active regions 3.
A gate oxide film 21 is formed on the surface of the active region 3. Then, the gate electrode interconnect line 4 is formed over the trench-type device isolation region 20 and the gate oxide film 21 (FIGS. 29 and 30).
The background art semiconductor device, however, encounters problems to be described below with reference to FIGS. 27 and 28. The insulating film 2a is formed by deposition, and the silicon oxide film 6 is formed by thermal oxidation. In general, the etching rate of an oxide film formed by thermal oxidation is lower than that of an oxide film formed by the CVD process. Thus, prior to the removal of the entire silicon oxide film 6, the insulating film 2a is etched away, and the sidewalls of the insulating film 2 are subsequently etched away. This creates depressions 22 positioned lower than the surface of the active region 3 at the outer edges of the trench-type device isolation region 20.
The presence of the depressions 22 causes drawbacks to be described below. Referring to FIG. 30, an electric field adjacent the center of the gate oxide film 21 is determined only by an electric field extending between the gate electrode interconnect line 4 and the active region 3 through the gate oxide film 21. On the other hand, an electric field adjacent the ends of the gate oxide film 21 is determined by an electric field extending between the gate electrode interconnect line 4 and the active region 3 through the gate oxide film 21 and an electric field extending between the gate electrode interconnect line 4 and the active region 3 through the trench-type device isolation region 20. The reduced thickness of the trench-type device isolation region 20 at its outer edges by the amount of the depressions 22 increases the influence of the electric field extending between the gate electrode interconnect line 4 and the active region 3 through the trench-type device isolation region 20. Then, the electric field adjacent the ends of the gate oxide film 21 is stronger than the electric field adjacent the center of the gate oxide film 21. This causes an effect reverse to the narrow channel effect, that is, the decrease in transistor threshold level. Additionally, with reference to FIG. 27, the insulating film 2a shaped by anisotropic etching has varied configurations. The variations in the configuration of the insulating film 2a give rise to variations in the size of the depressions 22, resulting in variations in the transistor threshold level.
Further, with reference to FIG. 29, the gate electrode interconnect line 4, when formed, flows into the depressions 22. Then, the active region 3 and the gate electrode interconnect line 4 become closer to each other and, at the worst, are short-circuited.
As above described, the presence of the depressions 22 exerts adverse influences such as the decrease in transistor threshold level and the short-circuit of the active region 3 and gate electrode interconnect line 4.